1. Technical Field
Various embodiments of the present disclosure relate to nonvolatile memory devices and methods of fabricating the same and, more particularly, to nonvolatile memory device having single-layered gates and methods of fabricating the same.
2. Related Art
Electrically erasable programmable read only memory (EEPROM) devices and flash memory devices are nonvolatile memory devices that retain their stored data even when their power supplies are interrupted. Various memory cell structures of the nonvolatile memory devices have been proposed to improve their performance. A typical unit memory cell of the nonvolatile memory devices employs a stack gate structure including a floating gate, an inter-gate dielectric layer and a control gate which are sequentially stacked on a semiconductor substrate. As electronic systems become smaller with the development of fabrication techniques of semiconductor devices, system-on-chip (SOC) products have been revealed and utilized as important devices of high performance digital systems. Each of the SOC products may include a plurality of semiconductor devices executing various functions in a single chip. For example, the SOC product may include at least one logic device and at least one memory device which are integrated in a single chip. Thus, fabrication technologies of embedded nonvolatile memory devices may be required to embed the nonvolatile memory devices in the SOC products.
To embed the nonvolatile memory devices in the SOC products, the process technology of the nonvolatile memory devices has to be compatible with the process technology of the logic device included in the SOC products. In general, the logic devices employ transistors having a single gate structure, whereas the nonvolatile memory devices employ cell transistors having a stack gate structure that is, a double gate structure. Thus, the SOC products including the nonvolatile memory devices and the logic devices may require a complicate process technology. Accordingly, single-layered gate nonvolatile memory devices employing a single-layered gate cell structure are very attractive as a candidate of the embedded nonvolatile memory devices. That is, complementary metal-oxide-semiconductor (CMOS) circuits of the logic devices may be readily realized using a process technology of the single-layered gate nonvolatile memory devices. As a result, the process technology of the single-layered gate nonvolatile memory devices may be widely used in fabrication of the SOC products including the embedded nonvolatile memory devices.